Hardware Reconfigurável para Controladores Nebulosos.

Abstract

Process control is one of the many applications that benefits from fuzzy control. In this kind of application, the controller is usually embedded in the controlled device. This dissertation proposes a reconfigurable architecture for efficient embedded fuzzy controllers. The architecture is customizable, as it allows the controller configuration to be used to implement any fuzzy model. The configuration parameters are: the number of input variables (N); the number of output variables (M); the number of linguistic terms (Q); and the total number of rules (P). The proposed architecture also enables the configuration of the characteristics that define the rules and membership functions of each input and output variable, allowing for an optimal scalability of the project. The composition of the antecedent and consequent of the rules are configurable, according to the fuzzy model that is being implemented. A priori, the architecture supports triangular membership functions, but it can be extended to accommodate other forms, such as trapezium, without major modifications. The characteristics of the lines, forming the membership functions of the linguistic terms, can be adjusted according to the definition of the fuzzy model, allowing the use of non-isosceles and isosceles triangles. Virtually, there are no limits on the number of rules or linguistic terms used in the model, as well as the number of input and output variables. The macro-architecture of the proposed controller is composed of N fuzzification blocks, 1 inference block, M defuzzification blocks and N blocks to handle the characteristics of the membership functions. This block operates only during the controller setup. The work done by the fuzzification blocks of the input variables is executed in parallel, as well as the computation performed by the defuzzification blocks of the output variables. The duplication of the fuzzification and defuzzification blocks accelerates the process of yielding the final response of the controller. Several simulations were performed to verify the correct operation of the controller, which is specified in VHDL. In a second stage, to evaluate the controller performance, the architecture was synthesized into a FPGA and tested with six applications to verify the reconfigurability and scalability of the design. The results obtained were compared with the ones obtained from MATLAB for each of the implemented applications, to demonstrate the accuracy of the controller.