Casamento de comprimento de trilhas de placas de circuito impresso utilizando otimização por colônia de formigas

Abstract

The advancement of electronic engineering has driven the miniaturization of electronic components and the increase in operating frequencies. Consequently, the electromagnetic tolerances and limitations associated with circuit geometry have become increasingly restrictive, creating new challenges in electronic system design. Automatic routing tools for Printed Circuit Boards (PCBs) and integrated circuits are essential to assist engineers and designers, optimizing time and resources. To address these challenges, strategies based on computational intelligence have been widely employed to obtain viable routing solutions efficiently. Among these strategies, multi-agent algorithms stand out for their relevance and versatility. In this work, we present a variation of the traditional Ant Colony Optimization (ACO) algorithm, modified to perform PCB routing with a focus on length matching of the circuit’s traces. The PCB area is divided into a grid that representes the algorithm’s search space. The routing of each trace is conducted by an individual ant colony, executed as an independent process. The ants of each colony traverse the path between the initial and final positions of a trace, seeking to identify the route that best satisfies a multi-objective optimization function. This function simultaneously minimizes three objectives: the total length of the traces, the number of crossings between traces, and the length difference between them. In other words, the ants aim to find the shortest possible route that maintains the same length as the other traces without crossing them. To evaluate these objectives, multiple heuristic strategies were applied. The proposed algorithm was implemented and tested in seven fundamental validation scenarios. The developed heuristics were analyzed and statistically compared based on the average results of hundreds of executions. Additionally, the program was applied to three scenarios derived from related works. The results demonstrate that the proposed approach is both viable and effective for PCB trace routing, meeting length matching requirements and contributing to solving design challenges.